Avinash Yadlapati Need OVM/VMM/System Verilog engineers with 3-10 years exp on an urgent basis. Please send resumes to avinash.amd@gmail.com asap
It ties well with our extended SystemVerilog classes from CVC, http://www.cvcblr.com wherein several mid-career engineers rehone their skills in Verification and get placed. A recent success is with Quartics @Pune.
Hello,
I joined Quartics last Friday. Have joined VLSI group here. The first thing I saw here is "A progmatic Approach to VMM Adoption" authored by you.
The training at CVC was very helpful. Got many interview calls after adding SV to my skill set.
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