ESC India launched in Pune!

Pune as a IT hub is very promising despite the slowdown etc. We at CVC delivered a VMM training recently. And few weeks back ESC (Embedded Systems Conference) launched its Pune chapter. So the well known "student city" is becoming an icon city for HW design as well.

Cheers
Ajeetha, CVC
www.noveldv.com

Pleasant surprise from Mentor for QVP partners

Suddenly we get a call from our courier saying they have a parcel from the US from MentorGraphics. Having got used to many such EDA shipments, I thought it is yet another CD/Software/datasheet. But as with their products - they gave me a nice surprise:



Again - without boasting so much, receiving a plaque is not that unusual for us/me. But the style, elegance and the nice little stand at the back all well planned, thoughout is what made me feel like writing about it here. As with their EDA tools - Mentor knows how to make things presentable and usable. Be it Modelsim/Questa or a QVP plaque, they pay attention to details, Kudos to Mentor!

News of Cadence and what it means to the VLSI industry

So you heard the BIG news of CDN. Sure it is a big bang, especially for those who look at it financially and from Wall street perspective (after all that's what matters when it comes to $). However I wanted to throw my view on what it means for an end user, VLSI design community etc. Precaution: I'm not an analyst with financial background, market watch etc. My views are more from technology perspective.

Taking a step back, here is a nice definition of the word "cadence" from Dictionary:

Music. a sequence of notes or chords that indicates the momentary end of a composition, section, phrase, etc.

So what we are perhaps seeing today is a "momentary end" of a composition than a dead-end (let's hope that for the benefit of VLSI/EDA industry). Some random rationale:

• Does this mean end of all Cadence products?
• Does it mean my CDN tools won't run any longer?
• Does it mean all the high end technologies inside IUS/Specman/SoC Encounter/RTL Compiler/Orcad etc. etc. is all heading for a trash can?

Clearly NOT! Infact the recent stats indicate that RC has been giving a tough time to competition. Specman for all its critics of a dead tool/language is instead alive and kicking. The E-language is being healthily balloted and new additions are on the making (If you like to participate, please visit: http://www.ieee1647.org/).

We have the likes of Ted Vucurevich (http://www.cadence.com/cadence/executive_team/Pages/bio_tvucurevich.aspx), ApurvaKalia (http://center.spoke.com/info/p9RaNk0/ApurvaKalia) et al. at Cadence.



SimVision has been one of the strongest ever built-in debuggers the EDA front end tools have ever seen. Specman still continues to be the UNBEATABLE HVL tool with its debugger, constraint solver (Look at the IntelliGen for instance).

Anyway, to summarize: it is not end of the world for EDA/CDN and the whole VLSI industry that relies on EDA. Make no mistake - it is a strong beating and effects shall be felt at a large Richter scale.

Ajeetha, CVC
www.noveldv.com

Free Seminar on " Quest for scalable Verification => result : OVM + Questa

Free Seminar on "Quest for Scalable Verification => result:Questa + OVM "

With ever growing complexities of ASICs (and FPGAs), the task of verifying them has become a “never-say-done” activity. Given the need for multiple levels of reuse in design and verification, a stand-still approach to verification doesn’t hold good any longer. It requires continuous inflow of new ideas, thoughts and technologies to address the complex requirements. Hence the quest for a scalable verification has been a continuous one. A series of innovative, path breaking technologies have emerged over the last decade to address the verification challenges. Back in 2005 IEEE standardized SystemVerilog as the standard HDVL to incorporate many of these technologies with a Verilog flavor. Since then SV has been making its way into being the most preferred language for ASIC Design and Verification across the globe. However leading edge semiconductor houses have quickly realized that using SystemVerilog on its own might lead to sub-optimal benefits especially in Verification. This is due to the fact that the language is vast and not every team has enough time to experiment with the right usage model for the task at hand. This is the primary motivation behind adopting a Verification Methodology - to get more productive in less time.

OVM as announced in late 2007/early 2008 is proving to be a very good choice for building such scalable verification infrastructure as it has all the classical methodology features plus some of the most advanced, proven verification techniques such as Virtual sequences, factories etc. The good thing about OVM is it is open, and there is a vibrant ecosystem building around OVM. We at CVC have an everlasting thirst to be on top of any new verification technology. As part of Mentor’s Questa Vanguard program, CVC has had the privilege of experiencing the power of OVM early with a robust, easy-to-use verification platform – Questa!

As with any new technology, the initial adoption requires some ramp up time. During our early engagements with building OVM compliant verification environments we went through a series of learning steps. As a result of it, we at CVC recently composed a step-by-step OVM quick start guide that we share with our customers. In this seminar, we share an early preview of this step-by-step guide with a simple packet de-serializer design. We walk through the following topics:

• SystemVerilog features for Verification
• OVM introduction
• DUV - Packet de-serializer
• Step-by-step OVM approach with code snippets
• Highlights of important Questa features that helped us in the process
• Results, summary and looking forward

To attend this seminar: Click on: Register for CVC OVM with Questa seminar. If the above link doesn’t work, send an email to mailto:cvc.training@gmail.com;?subject=CVC_OVM_Questa Please include the following details in your email.

Name:
Company Name:
Official Email ID:
Contact Number:

Venue: CVC Bangalore Office (Ground Floor)

Date: 2^nd Aug 2008, Saturday at 15.00 (3.00 PM)

Agenda: 1 hour presentation followed by a quick demo + Q&A

Fast-Track course on Verification Using SystemVerilog - Bangalore

Fast-Track course on Verification Using SystemVerilog - Bangalore

Quick facts

When: 6^th or 7^th June (Fri/Sat)

Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Cost: Rs. 2500 /- onwards (See below for details)

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?

IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?

A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?

Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?

That is a no-brainer question, isn’t it? We understand and appreciate the cost conscious landscape of our region. That’s why we have innovative cost structure as shown below.

The basic cost of this course is Rs. 4,000 /- per attendee. As a limited period offer, we are glad to announce “The more-the-merrier” scheme. If you pool in more folks you get more discounts. For every other attendee that you bring along, you get Rs. 500 /- discount – for BOTH the attendees (subjected to a minimum of Rs. 2500 /-), can it get better than this :-) ?

Here is a simple table showing the offer in numeric:

No. of attendees | Cost per attendee | Your savings (total)

2 3500 1000

3 3000 3000

4 (and above) 2500 6000+

Venue details

CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:

Friday 6^th June at 8.30 AM

Saturday 7^th June at 8.30 AM

How do I register for a class?

To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572

Please include the following details in your email:

Name:
Company Name:
Official Email ID:
Contact Number:

Preferred Date: 6^th or 7^th June (Friday or Saturday)

Are there extended versions of these courses?

Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:

• · A 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
• · A 3-day class and
• · A 2-day class

So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile
Ajeetha Kumari, Design Verification Consultant
* Has 8+ years of experience in Verification
* Co-authored leading books in the Verification domain.
* Presented papers, tutorials in various conferences, publications and
avenues.
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV
and OOP for Verification
* Holds M.S.E.E. from prestigious IIT, Madras.

12th IEEE VLSI Design And Test Symposium

12^th IEEE VLSI Design And Test Symposium

VDAT2008, the 12^th IEEE VLSI Design And Test Symposium is scheduled during July 23-26, 2008, at the Wipro Campus, Electronics city, Bangalore.

Visit VDAT2008 webpage for details.

Workshop on VLSI AND EMBEDDED SYSTEMS, NIT Calicut

CVC (www.noveldv.com) is presenting an introduction to Design Verification at NIT Calicut.

15 June 2008 to 28th June 2008

http://www.nitc.ac.in/nitc/fdp/Schedule_STTP.htm
Topics:
VLSI: VLSI Physical Design Automation - Introduction to VLSI CAD, VLSI Signal Integrity, Mixed Signal VLSI Design and Test, Reconfigurable Systems and Applications, Low Power Design Techniques, Recent Advances in Memory Technology, Design and Test
Challenges in Analog Design, Challenges in IO Design, Design for Testability - Theory and Practice, Design Verification Methodologies
Embedded Systems: Embedded Sytems Overview: Design Metrics and Challenges, Standard and Custom Single purpose processors and Peripherals, State Machine and Concurrent Process Models, Design Technology, Verification, Embedded Design Patterns, Real Time Operating systems