Monday, February 16, 2009

Update your skills to beat recession – from Dice.com

An excellent piece of advice and backed with statistics from dice.com. It is extremely important to keep yourself upto-date in VLSI field too. BTW, CVC offers the relveant training on VLSI functional verification, see: sv-verif.blogspot.com for upcoming classes.

Electronic Business: How do the top worries for technology professionals in 2009 compare to those in last year's survey results? Was "keeping skills up to date" at the top last year?
Silver: We didn’t ask that question last year, however, we’ve asked similar questions many times and keeping skills up to date is always a huge concern for technology professionals. There is an obsolescence issue with technology. In order to stay relevant and continue to increase your earnings potential, adding skills is the most direct path to higher compensation. Updating and broadening one’s skill set is important in any economy, but with the job market softening and the economy declining, technology professionals need to be as up to date as possible to have the best chance at a new job should they fall victim to a layoff.

Answer

Responses  from total survery, %

Responses from EEs only, %

Keeping skills up-to-date/being valuable to employer

22%

23%

Position elimination

20%

21%
….    
     
     
     
     

http://www.edn.com/article/CA6637653.html

Wednesday, February 11, 2009

Certificate course on Functional Verification …basics to ASIC verification using SystemVerilog

Certificate course on

Functional Verification

…basics to ASIC

verification using

SystemVerilog

CVC is about to launch a 10-day certificate course on Functional Verification covering SystemVerilog in depth. Broadly it covers the following topics:

  • Comprehensive introduction to Functional Verification (CFV)
  • SystemVerilog basics (SVB)
  • SystemVerilog Assertion (SVA)
  • Verification Using SystemVerilog (VSV)
  • Verification Methodology (VM)

Duration

Here is a detailed breakdown of the course with duration. Note that we have several “mini projects” tightly embedded in the course that helps in mastering topics learned so far in the course. This is on top of the regular labs that are part of the training. The detailed breakup of topics and labs is covered in next sections of this proposal.

Topic

Duration

Comprehensive Functional Verification

1.5 days

Mini Project I

0.5 day

SystemVerilog Basics

0.5 day

SystemVerilog Assertions

1.5 days

Mini Project II

0.5 day

Verification using SystemVerilog

2.0 days

Mini Project III

0.5 day

Verification Methodology

2.0 days

Project IV

1.0 day

Schedule

Tentative: Feb 09-Mar09

Contact

Send an email to: cvc.training@gmail.com and/or training@noveldv.com for more details, cost etc. Or call us at: +91-9916176014