Update your skills to beat recession – from Dice.com

An excellent piece of advice and backed with statistics from dice.com. It is extremely important to keep yourself upto-date in VLSI field too. BTW, CVC offers the relveant training on VLSI functional verification, see: sv-verif.blogspot.com for upcoming classes.

Electronic Business: How do the top worries for technology professionals in 2009 compare to those in last year's survey results? Was "keeping skills up to date" at the top last year?
Silver: We didn’t ask that question last year, however, we’ve asked similar questions many times and keeping skills up to date is always a huge concern for technology professionals. There is an obsolescence issue with technology. In order to stay relevant and continue to increase your earnings potential, adding skills is the most direct path to higher compensation. Updating and broadening one’s skill set is important in any economy, but with the job market softening and the economy declining, technology professionals need to be as up to date as possible to have the best chance at a new job should they fall victim to a layoff.

Answer	Responses  from total survery, %	Responses from EEs only, %
Keeping skills up-to-date/being valuable to employer	22%	23%
Position elimination	20%	21%
….

http://www.edn.com/article/CA6637653.html

Certificate course on Functional Verification …basics to ASIC verification using SystemVerilog

Certificate course on

Functional Verification

…basics to ASIC

verification using

SystemVerilog

CVC is about to launch a 10-day certificate course on Functional Verification covering SystemVerilog in depth. Broadly it covers the following topics:

• Comprehensive introduction to Functional Verification (CFV)
• SystemVerilog basics (SVB)
• SystemVerilog Assertion (SVA)
• Verification Using SystemVerilog (VSV)
• Verification Methodology (VM)

Duration

Here is a detailed breakdown of the course with duration. Note that we have several “mini projects” tightly embedded in the course that helps in mastering topics learned so far in the course. This is on top of the regular labs that are part of the training. The detailed breakup of topics and labs is covered in next sections of this proposal.

Topic	Duration
Comprehensive Functional Verification	1.5 days
Mini Project I	0.5 day
SystemVerilog Basics	0.5 day
SystemVerilog Assertions	1.5 days
Mini Project II	0.5 day
Verification using SystemVerilog	2.0 days
Mini Project III	0.5 day
Verification Methodology	2.0 days
Project IV	1.0 day

Schedule

Tentative: Feb 09-Mar09

Contact

Send an email to: cvc.training@gmail.com and/or training@noveldv.com for more details, cost etc. Or call us at: +91-9916176014

Excerpts on Recession, IT industry and students’ choices

 

Education Plus The HINDU

Time to upgrade/hone your skills!

…”The industry and the market will definitely look up and in the meantime the students should not lose focus. They should utilise the time to upgrade themselves with higher education. The IT boom had relatively closed the door for higher education and it is now time to get back to it,” says the Secretary of GVP.

 

Keeping aside dreams of financial independence, several freshers are looking at sharpening their resumes with certificate courses.

“Upgrade and wait till the temporary phase ends” to emerge stronger.

-----------------

Emphasis will also be given to IT education. This will help the state develop a talent pool, so that when the downturn ends, it will be ready to cater to the needs of the industry.

……………..West Bengal IT Minister Debesh Das

Need for specialized courses

Industry sources want the leading private institutions to introduce a one-year PG programme for IT students passing out of their colleges this year

“Since recruitments are expected to be on a low side, and the students need to be gainfully occupied till the industry recovers,

 

Predicted recovery

“…Students should shape their skills for employment in 2010,” reasons a communications manager of a leading IT company.

It is estimated that by 2010 things will look up and the students should utilise this time by taking up higher studies. All these years we have been floating in a bubble and the actual scenario will surface, post recession. Hence, students should arm themselves with sufficient subject knowledge, to take the first 15 per cent cream of the renewed IT sector,”

  -- Placement officer of Andhra University

Recession and existing VLSI workforce – quotes from industry watch

The IT sector can never crash, as still 95 per cent of its area is left unexplored. The recession is only a temporary phase... The people who are on the bench need not get depressed and instead work on improving their skills.

--- The Vice-Chancellor of JNTU

 

“For the excess resources, the option of going on leave without pay for higher studies or pursuing other interests has been provisioned,” Head of HR Practices @Sasken explained.

 

ESC India launched in Pune!

Pune as a IT hub is very promising despite the slowdown etc. We at CVC delivered a VMM training recently. And few weeks back ESC (Embedded Systems Conference) launched its Pune chapter. So the well known "student city" is becoming an icon city for HW design as well.

Cheers
Ajeetha, CVC
www.noveldv.com

Pleasant surprise from Mentor for QVP partners

Suddenly we get a call from our courier saying they have a parcel from the US from MentorGraphics. Having got used to many such EDA shipments, I thought it is yet another CD/Software/datasheet. But as with their products - they gave me a nice surprise:



Again - without boasting so much, receiving a plaque is not that unusual for us/me. But the style, elegance and the nice little stand at the back all well planned, thoughout is what made me feel like writing about it here. As with their EDA tools - Mentor knows how to make things presentable and usable. Be it Modelsim/Questa or a QVP plaque, they pay attention to details, Kudos to Mentor!

News of Cadence and what it means to the VLSI industry

So you heard the BIG news of CDN. Sure it is a big bang, especially for those who look at it financially and from Wall street perspective (after all that's what matters when it comes to $). However I wanted to throw my view on what it means for an end user, VLSI design community etc. Precaution: I'm not an analyst with financial background, market watch etc. My views are more from technology perspective.

Taking a step back, here is a nice definition of the word "cadence" from Dictionary:

Music. a sequence of notes or chords that indicates the momentary end of a composition, section, phrase, etc.

So what we are perhaps seeing today is a "momentary end" of a composition than a dead-end (let's hope that for the benefit of VLSI/EDA industry). Some random rationale:

• Does this mean end of all Cadence products?
• Does it mean my CDN tools won't run any longer?
• Does it mean all the high end technologies inside IUS/Specman/SoC Encounter/RTL Compiler/Orcad etc. etc. is all heading for a trash can?

Clearly NOT! Infact the recent stats indicate that RC has been giving a tough time to competition. Specman for all its critics of a dead tool/language is instead alive and kicking. The E-language is being healthily balloted and new additions are on the making (If you like to participate, please visit: http://www.ieee1647.org/).

We have the likes of Ted Vucurevich (http://www.cadence.com/cadence/executive_team/Pages/bio_tvucurevich.aspx), ApurvaKalia (http://center.spoke.com/info/p9RaNk0/ApurvaKalia) et al. at Cadence.



SimVision has been one of the strongest ever built-in debuggers the EDA front end tools have ever seen. Specman still continues to be the UNBEATABLE HVL tool with its debugger, constraint solver (Look at the IntelliGen for instance).

Anyway, to summarize: it is not end of the world for EDA/CDN and the whole VLSI industry that relies on EDA. Make no mistake - it is a strong beating and effects shall be felt at a large Richter scale.

Ajeetha, CVC
www.noveldv.com